Detail
Feb 13

Asociación Centro Tecnológico Ceit-IK4 (Ceit-IK4)- Spain

Ceit-IK4 is a private multidisciplinary non-profit RTO closely connected to TECNUN, the School of Engineering of the University of Navarra (Spain). Its missions are to provide industry with services through the development of technical research projects and to promote the dissemination of knowledge through the training of young researchers and PhD students and scientific publications.

Regarding our first mission, more than 100 research projects between TRL4 and TRL7 are carried out at Ceit-IK4 per year. Moreover, Ceit-IK4 has participated in 15 FP6 projects, 32 FP7 projects, 18 RFCS projects, 3 LIFE project and, for the moment, in 37 H2020 projects, out of which 10 are coordinated.
In terms of our second mission, in the last 5 years Ceit-IK4 has produced more than 30 PhD theses per year, published 100 papers in scientific journals, and participated in 80 international conferences.
Since 1996 Ceit-IK4 has created 15 technology-based spin-offs, which currently employ more than 300 people. Four of these have been purchased by companies which are listed on NASDAQ, NYSE, the Madrid Stock Exchange and the Paris Stock Exchange.
Ceit-IK4 has a staff of over 260 employees and 45 PhD students, and an annual budget over 16.5 M€. Ceit-IK4 consists of three vertical divisions (Materials and Manufacturing, Transport and Energy, Water and Health) and a fourth additional horizontal division (ICT). In this project, the ICT division will be involved.
The ICT division of CEIT has a wide experience in wireless communication systems. In previous projects, CEIT has been involved in tasks related to architecture analysis, to design and implementation of digital modems, to design and implementation of analogue front-end ICs and to integration for ultra-wide band and mmW. CEIT has already designed circuits for mmW application using the 55nm BiCMOS technology of ST.

Main tasks in the project

In the project, CEIT will collaborate in the system specification and in the architecture definition within WP1. CEIT will participate in WP2 designing blocks for the analogue front-end ICs using ST 55 nm SiGe technology and it will be responsible for the integration of the antenna array driver chips. CEIT will provide support to the activities in WP3, WP4 and WP5 regarding the interaction with the ICs developed in WP2.

www.ceit.es/en/

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