Feb 14

University of Pavia (UniPV) – ITALY

 The University of Pavia (UniPV) is one of the oldest in Europe, founded in 825. Many renowned humanists and scientists studied and taught at the Alma Ticinensis Universitas, such as Cardano, the inventor of the Cardanic joint, and Alessandro Volta, the inventor of electric battery. The Department of Electrical, Computer and Biomedical Engineering hosts 80 professors with internationally recognized scientific profile which are active in the research fields of microelectronics, bio-engineering and computer science. Many groups in the Department have established and proved experience in developing new analog and high speed (RF, mmW) integrated circuits. Thanks to the intense activity in this field, UniPV is present almost every year at the IEEE International Solid State Circuit Conference (ISSCC), discovering new achievements. The scientific production of high-profile, internationally widespread in recent years, places UniPV in the top universities worldwide within the research field of integrated circuits.
Most of the research activity will be carried out within the Analog Integrated Circuits Lab, which involves an average of 10 researchers in the position of MS students, PhDs and Post doc. UniPV hosts also the Studio di Microelettronica, a research laboratory funded by STMicroelectronics that favour the cooperation between STM engineers and University professors on common research activities and speed-up the training of young graduate students.

Main tasks in the project

The primary role of UPV within the project is the design of the Local Oscillator generation circuits for the D-band transceiver and investigation of new circuit architectures for improving performances with the BiCMOS 55nm technology. UniPV will also coordinate the dissemination and exploitation activities of the project.
More in detail, UniPV will contribute to the following work packages:

  • WP1: Applications, Technology Specifications and Architectures. UniPV will contribute to the definition
    of the architecture and specifications, considering the issues and constraints related the LO generation
  • WP2: Radio analog front end. UniPV will contribute by designing and testing the LO generation chain for
    the D-band transceiver. And by investigating, in the second part of the project, novel architectures or circuit.
    solutions to improve performances of critical building blocks for the D-band radio chip set.
  • WP6: Dissemination, Exploitation, Standardization and Regulation. UniPV will coordinate these activities
    as WP leader. UniPV will contribute to dissemination through scientific papers and by promoting the project to students, researchers and professors worldwide by leveraging different communication channels.

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